8086 microprocessor Divided into two functional units which work simultaneously to increase system speed and throughput (inst. exe. per unit time)
- Bus Interface Unit
- Execution Unit
- Bus Interface Unit – Interface to outside world and responsible for all external operations e.g
–Fetches instructions from memory and data from mem./port
–Supports instruction queue and address relocation facility.
–QUEUE – SIX instruction bytes are fetched ahead of time (FIFO)
- Execution Unit – works in parallel to BIU and responsible for
–Execution of Instructions, providing address to BIU for fetching data/instructions
–Manipulating various registers including FLAG register.
Functional unit contains –
–Control circuits and instruction decoders
–ALU, FLAG Register, GPRs, SP, Pointers and Index register
Block diagram of 8086 microprocessor
- to speedup program execution.
- the pre fetched instruction are held for EU.
- simultaneous work is done i.e. fetching & executing.
- except in case of JUMP & CALL where the queue is dumped and reloaded.
- fetching next instruction while the current instruction is under execution is called pipelining.
Register Organization of 8086
- General Data Registers (AX, BX, CX, DX), AX is Accumulator
- Segment Registers (CS, SS, DS, ES)
- Pointer & Indexed Registers (SP, BP, SI, DI, IP)
- CS register points to the base or start of the current code segment and the IP contains the distance or offset from this base address to fetch the next instruction byte.
- The 8086 20-bit physical address is often represented in a segment base: offset form rather than in single no. form. CS:IP. e.g. 348A:4214.